Fyntv Instruction Set Architecture

Reference Manual

Version: 0.0.0.1 | Date: June 2026

Registers

Register	ABI Name	Description	Saved
x0	zero	Always-zero register — reads return 0, writes are discarded	No
x1	ra	Return address link register	No
x2	sp	Stack pointer	Yes
x3	gp	Global pointer	Yes
x4	tp	Thread pointer	Yes
x5	t0	Temporary register 0	No
x6	t1	Temporary register 1	No
x7	t2	Temporary register 2	No
x8	s0	Saved register 0 / frame pointer	Yes
x9	s1	Saved register 1	Yes
x10	a0	Function argument 0 / return value 0	No
x11	a1	Function argument 1 / return value 1	No
x12	a2	Function argument 2	No
x13	a3	Function argument 3	No
x14	a4	Function argument 4	No
x15	a5	Function argument 5	No
x16	a6	Function argument 6	No
x17	a7	Function argument 7	No
x18	s2	Saved register 2	Yes
x19	s3	Saved register 3	Yes
x20	s4	Saved register 4	Yes
x21	s5	Saved register 5	Yes
x22	s6	Saved register 6	Yes
x23	s7	Saved register 7	Yes
x24	s8	Saved register 8	Yes
x25	s9	Saved register 9	Yes
x26	s10	Saved register 10	Yes
x27	s11	Saved register 11	Yes
x28	t3	Temporary register 3	No
x29	t4	Temporary register 4	No
x30	t5	Temporary register 5	No
x31	t6	Temporary register 6	No

Instruction Set

Mnemonic	Format	Opcode	Operands	Description
`ADD`	R	`0x33`	`rd, rs1, rs2`	Add registers
`SUB`	R	`0x33`	`rd, rs1, rs2`	Subtract registers
`ADDI`	I	`0x13`	`rd, rs1, imm12`	Add sign-extended 12-bit immediate to register rs1
`SLT`	R	`0x33`	`rd, rs1, rs2`	Set if rs1 is less than rs2 (signed)
`SLTU`	R	`0x33`	`rd, rs1, rs2`	Set if rs1 is less than rs2 (unsigned)
`SLTI`	I	`0x13`	`rd, rs1, imm12`	Set if rs1 is less than immediate (signed)
`SLTIU`	I	`0x13`	`rd, rs1, imm12`	Set if rs1 is less than immediate (unsigned)
`LUI`	U	`0x37`	`rd, imm20`	Load upper immediate — places 20-bit immediate in upper 20 bits of rd
`AUIPC`	U	`0x17`	`rd, imm20`	Add upper immediate to PC — forms PC-relative address
`AND`	R	`0x33`	`rd, rs1, rs2`	Bitwise AND
`OR`	R	`0x33`	`rd, rs1, rs2`	Bitwise OR
`XOR`	R	`0x33`	`rd, rs1, rs2`	Bitwise XOR
`ANDI`	I	`0x13`	`rd, rs1, imm12`	Bitwise AND with immediate
`ORI`	I	`0x13`	`rd, rs1, imm12`	Bitwise OR with immediate
`XORI`	I	`0x13`	`rd, rs1, imm12`	Bitwise XOR with immediate
`SLL`	R	`0x33`	`rd, rs1, rs2`	Logical left shift by lower 5 bits of rs2
`SRL`	R	`0x33`	`rd, rs1, rs2`	Logical right shift by lower 5 bits of rs2
`SRA`	R	`0x33`	`rd, rs1, rs2`	Arithmetic right shift by lower 5 bits of rs2
`SLLI`	I	`0x13`	`rd, rs1, shamt5`	Logical left shift by immediate shift amount
`SRLI`	I	`0x13`	`rd, rs1, shamt5`	Logical right shift by immediate shift amount
`SRAI`	I	`0x13`	`rd, rs1, shamt5`	Arithmetic right shift by immediate shift amount
`LB`	I	`0x03`	`rd, offset(rs1)`	Load byte (sign-extended)
`LH`	I	`0x03`	`rd, offset(rs1)`	Load halfword (sign-extended)
`LW`	I	`0x03`	`rd, offset(rs1)`	Load word
`LBU`	I	`0x03`	`rd, offset(rs1)`	Load byte (zero-extended)
`LHU`	I	`0x03`	`rd, offset(rs1)`	Load halfword (zero-extended)
`SB`	S	`0x23`	`rs2, offset(rs1)`	Store byte
`SH`	S	`0x23`	`rs2, offset(rs1)`	Store halfword
`SW`	S	`0x23`	`rs2, offset(rs1)`	Store word
`BEQ`	B	`0x63`	`rs1, rs2, label`	Branch equal
`BNE`	B	`0x63`	`rs1, rs2, label`	Branch not equal
`BLT`	B	`0x63`	`rs1, rs2, label`	Branch less than (signed)
`BGE`	B	`0x63`	`rs1, rs2, label`	Branch greater than or equal (signed)
`BLTU`	B	`0x63`	`rs1, rs2, label`	Branch less than (unsigned)
`BGEU`	B	`0x63`	`rs1, rs2, label`	Branch greater than or equal (unsigned)
`JAL`	J	`0x6F`	`rd, label`	Jump and link — jump to PC+offset, save return address to rd
`JALR`	I	`0x67`	`rd, rs1, offset`	Jump and link register — jump to rs1+offset, save return address
`FENCE`	I	`0x0F`	`pred, succ`	Memory ordering fence
`FENCEI`	I	`0x0F`	`—`	Instruction fence — synchronizes instruction and data streams
`ECALL`	I	`0x73`	`—`	Environment call — raises a system call exception
`EBREAK`	I	`0x73`	`—`	Breakpoint — raises a breakpoint exception
`CSRRW`	I	`0x73`	`rd, csr, rs1`	Atomic read/write CSR — writes rs1 to CSR, returns old value in rd
`CSRRS`	I	`0x73`	`rd, csr, rs1`	Atomic read and set bits in CSR
`CSRRC`	I	`0x73`	`rd, csr, rs1`	Atomic read and clear bits in CSR
`CSRRWI`	I	`0x73`	`rd, csr, uimm5`	Atomic read/write CSR with immediate
`CSRRSI`	I	`0x73`	`rd, csr, uimm5`	Atomic read and set bits in CSR with immediate
`CSRRCI`	I	`0x73`	`rd, csr, uimm5`	Atomic read and clear bits in CSR with immediate