# Fyntv Control and Status Register Definitions

CSR mstatus
  NUMBER 0x300
  DESC Machine status register — holds global interrupt enable and privilege state
END

CSR misa
  NUMBER 0x301
  DESC Machine ISA register — encodes supported ISA extensions
END

CSR medeleg
  NUMBER 0x302
  DESC Machine exception delegation register
END

CSR mideleg
  NUMBER 0x303
  DESC Machine interrupt delegation register
END

CSR mie
  NUMBER 0x304
  DESC Machine interrupt-enable register
END

CSR mtvec
  NUMBER 0x305
  DESC Machine trap-handler base address
END

CSR mcounteren
  NUMBER 0x306
  DESC Machine counter enable register
END

CSR mscratch
  NUMBER 0x340
  DESC Scratch register for machine-mode trap handlers
END

CSR mepc
  NUMBER 0x341
  DESC Machine exception program counter — holds PC of trapping instruction
END

CSR mcause
  NUMBER 0x342
  DESC Machine trap cause — encodes exception or interrupt cause
END

CSR mtval
  NUMBER 0x343
  DESC Machine trap value — exception-specific information
END

CSR mip
  NUMBER 0x344
  DESC Machine interrupt pending register
END

CSR pmpcfg0
  NUMBER 0x3A0
  DESC Physical memory protection configuration 0
END

CSR pmpaddr0
  NUMBER 0x3B0
  DESC Physical memory protection address 0
END

CSR pmpaddr1
  NUMBER 0x3B1
  DESC Physical memory protection address 1
END

CSR pmpaddr2
  NUMBER 0x3B2
  DESC Physical memory protection address 2
END

CSR pmpaddr3
  NUMBER 0x3B3
  DESC Physical memory protection address 3
END

CSR mcycle
  NUMBER 0xB00
  DESC Machine cycle counter — counts number of clock cycles
END

CSR minstret
  NUMBER 0xB02
  DESC Machine instructions-retired counter
END

CSR mhpmcounter3
  NUMBER 0xB03
  DESC Machine hardware performance counter 3
END

CSR mhpmcounter4
  NUMBER 0xB04
  DESC Machine hardware performance counter 4
END

CSR mhpmcounter5
  NUMBER 0xB05
  DESC Machine hardware performance counter 5
END

CSR mhpmevent3
  NUMBER 0x323
  DESC Machine hardware performance event selector 3
END

CSR mhpmevent4
  NUMBER 0x324
  DESC Machine hardware performance event selector 4
END

CSR mhpmevent5
  NUMBER 0x325
  DESC Machine hardware performance event selector 5
END

CSR ucycle
  NUMBER 0xC00
  DESC User-mode cycle counter read
END

CSR uinstret
  NUMBER 0xC02
  DESC User-mode instructions-retired read
END

CSR ucycleh
  NUMBER 0xC80
  DESC Upper 32 bits of user-mode cycle counter
END

CSR uinstreth
  NUMBER 0xC82
  DESC Upper 32 bits of user-mode instructions-retired counter
END

CSR sstatus
  NUMBER 0x100
  DESC Supervisor status register
END

CSR sie
  NUMBER 0x104
  DESC Supervisor interrupt-enable register
END

CSR stvec
  NUMBER 0x105
  DESC Supervisor trap-handler base address
END

CSR sscratch
  NUMBER 0x140
  DESC Scratch register for supervisor-mode trap handlers
END

CSR sepc
  NUMBER 0x141
  DESC Supervisor exception program counter
END

CSR scause
  NUMBER 0x142
  DESC Supervisor trap cause register
END

CSR stval
  NUMBER 0x143
  DESC Supervisor trap value register
END

CSR sip
  NUMBER 0x144
  DESC Supervisor interrupt pending register
END

CSR satp
  NUMBER 0x180
  DESC Supervisor address translation and protection — controls page tables
END