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diff --git a/gen/docs/isa_defs/arch.isa b/gen/docs/isa_defs/arch.isa
new file mode 100644
index 0000000..f1added
--- /dev/null
+++ b/gen/docs/isa_defs/arch.isa
@@ -0,0 +1,68 @@
+# Fyntv Architecture Definition
+ARCH Fyntv
+  NAME Fyntv
+  VERSION 0.0.0.1
+  DATE June 2026
+  STATUS Draft
+END
+
+# =============================================================================
+# Instruction Formats
+# =============================================================================
+
+FORMAT R
+  WIDTH 32
+  FIELD opcode  6:0
+  FIELD rd      11:7
+  FIELD funct3  14:12
+  FIELD rs1     19:15
+  FIELD rs2     24:20
+  FIELD funct7  31:25
+END
+
+FORMAT I
+  WIDTH 32
+  FIELD opcode  6:0
+  FIELD rd      11:7
+  FIELD funct3  14:12
+  FIELD rs1     19:15
+  FIELD imm     31:20
+END
+
+FORMAT S
+  WIDTH 32
+  FIELD opcode  6:0
+  FIELD imm_lo  11:7
+  FIELD funct3  14:12
+  FIELD rs1     19:15
+  FIELD rs2     24:20
+  FIELD imm_hi  31:25
+END
+
+FORMAT B
+  WIDTH 32
+  FIELD opcode  6:0
+  FIELD imm_4_1 11:7
+  FIELD funct3  14:12
+  FIELD rs1     19:15
+  FIELD rs2     24:20
+  FIELD imm_10_5 30:25
+  FIELD imm_12  31:31
+END
+
+FORMAT U
+  WIDTH 32
+  FIELD opcode  6:0
+  FIELD rd      11:7
+  FIELD imm     31:12
+END
+
+FORMAT J
+  WIDTH 32
+  FIELD opcode  6:0
+  FIELD rd      11:7
+  FIELD imm_19_12 19:12
+  FIELD imm_11  20:20
+  FIELD imm_10_1 30:21
+  FIELD imm_20  31:31
+END
diff --git a/gen/docs/isa_defs/csrs.isa b/gen/docs/isa_defs/csrs.isa
new file mode 100644
index 0000000..e2098ef
--- /dev/null
+++ b/gen/docs/isa_defs/csrs.isa
@@ -0,0 +1,191 @@
+# Fyntv Control and Status Register Definitions
+
+CSR mstatus
+  NUMBER 0x300
+  DESC Machine status register — holds global interrupt enable and privilege state
+END
+
+CSR misa
+  NUMBER 0x301
+  DESC Machine ISA register — encodes supported ISA extensions
+END
+
+CSR medeleg
+  NUMBER 0x302
+  DESC Machine exception delegation register
+END
+
+CSR mideleg
+  NUMBER 0x303
+  DESC Machine interrupt delegation register
+END
+
+CSR mie
+  NUMBER 0x304
+  DESC Machine interrupt-enable register
+END
+
+CSR mtvec
+  NUMBER 0x305
+  DESC Machine trap-handler base address
+END
+
+CSR mcounteren
+  NUMBER 0x306
+  DESC Machine counter enable register
+END
+
+CSR mscratch
+  NUMBER 0x340
+  DESC Scratch register for machine-mode trap handlers
+END
+
+CSR mepc
+  NUMBER 0x341
+  DESC Machine exception program counter — holds PC of trapping instruction
+END
+
+CSR mcause
+  NUMBER 0x342
+  DESC Machine trap cause — encodes exception or interrupt cause
+END
+
+CSR mtval
+  NUMBER 0x343
+  DESC Machine trap value — exception-specific information
+END
+
+CSR mip
+  NUMBER 0x344
+  DESC Machine interrupt pending register
+END
+
+CSR pmpcfg0
+  NUMBER 0x3A0
+  DESC Physical memory protection configuration 0
+END
+
+CSR pmpaddr0
+  NUMBER 0x3B0
+  DESC Physical memory protection address 0
+END
+
+CSR pmpaddr1
+  NUMBER 0x3B1
+  DESC Physical memory protection address 1
+END
+
+CSR pmpaddr2
+  NUMBER 0x3B2
+  DESC Physical memory protection address 2
+END
+
+CSR pmpaddr3
+  NUMBER 0x3B3
+  DESC Physical memory protection address 3
+END
+
+CSR mcycle
+  NUMBER 0xB00
+  DESC Machine cycle counter — counts number of clock cycles
+END
+
+CSR minstret
+  NUMBER 0xB02
+  DESC Machine instructions-retired counter
+END
+
+CSR mhpmcounter3
+  NUMBER 0xB03
+  DESC Machine hardware performance counter 3
+END
+
+CSR mhpmcounter4
+  NUMBER 0xB04
+  DESC Machine hardware performance counter 4
+END
+
+CSR mhpmcounter5
+  NUMBER 0xB05
+  DESC Machine hardware performance counter 5
+END
+
+CSR mhpmevent3
+  NUMBER 0x323
+  DESC Machine hardware performance event selector 3
+END
+
+CSR mhpmevent4
+  NUMBER 0x324
+  DESC Machine hardware performance event selector 4
+END
+
+CSR mhpmevent5
+  NUMBER 0x325
+  DESC Machine hardware performance event selector 5
+END
+
+CSR ucycle
+  NUMBER 0xC00
+  DESC User-mode cycle counter read
+END
+
+CSR uinstret
+  NUMBER 0xC02
+  DESC User-mode instructions-retired read
+END
+
+CSR ucycleh
+  NUMBER 0xC80
+  DESC Upper 32 bits of user-mode cycle counter
+END
+
+CSR uinstreth
+  NUMBER 0xC82
+  DESC Upper 32 bits of user-mode instructions-retired counter
+END
+
+CSR sstatus
+  NUMBER 0x100
+  DESC Supervisor status register
+END
+
+CSR sie
+  NUMBER 0x104
+  DESC Supervisor interrupt-enable register
+END
+
+CSR stvec
+  NUMBER 0x105
+  DESC Supervisor trap-handler base address
+END
+
+CSR sscratch
+  NUMBER 0x140
+  DESC Scratch register for supervisor-mode trap handlers
+END
+
+CSR sepc
+  NUMBER 0x141
+  DESC Supervisor exception program counter
+END
+
+CSR scause
+  NUMBER 0x142
+  DESC Supervisor trap cause register
+END
+
+CSR stval
+  NUMBER 0x143
+  DESC Supervisor trap value register
+END
+
+CSR sip
+  NUMBER 0x144
+  DESC Supervisor interrupt pending register
+END
+
+CSR satp
+  NUMBER 0x180
+  DESC Supervisor address translation and protection — controls page tables
+END
diff --git a/gen/docs/isa_defs/instructions.isa b/gen/docs/isa_defs/instructions.isa
new file mode 100644
index 0000000..c7255d3
--- /dev/null
+++ b/gen/docs/isa_defs/instructions.isa
@@ -0,0 +1,512 @@
+# Fyntv Core Integer Instructions
+
+INSTRUCTION ADD
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x0
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Add registers
+  NOTE rd = rs1 + rs2
+  CATEGORY Integer
+END
+
+INSTRUCTION SUB
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x0 
+  FUNCT7 0x20
+  OPERANDS rd, rs1, rs2
+  DESC Subtract registers
+  NOTE rd = rs1 - rs2
+  CATEGORY Integer
+END
+
+INSTRUCTION ADDI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x0
+  OPERANDS rd, rs1, imm12
+  DESC Add sign-extended 12-bit immediate to register rs1
+  NOTE rd = rs1 + sext(imm12)
+  CATEGORY Integer
+  IMM true
+END
+
+INSTRUCTION SLT
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x2
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Set if rs1 is less than rs2 (signed)
+  NOTE rd = (rs1 < rs2) ? 1 : 0
+  CATEGORY Integer
+END
+
+INSTRUCTION SLTU
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x3
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Set if rs1 is less than rs2 (unsigned)
+  NOTE rd = (rs1 < rs2) ? 1 : 0
+  CATEGORY Integer
+END
+
+INSTRUCTION SLTI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x2
+  OPERANDS rd, rs1, imm12
+  DESC Set if rs1 is less than immediate (signed)
+  NOTE rd = (rs1 < sext(imm12)) ? 1 : 0
+  CATEGORY Integer
+  IMM true
+END
+
+INSTRUCTION SLTIU
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x3
+  OPERANDS rd, rs1, imm12
+  DESC Set if rs1 is less than immediate (unsigned)
+  NOTE rd = (rs1 < sext(imm12)) ? 1 : 0
+  CATEGORY Integer
+  IMM true
+END
+
+INSTRUCTION LUI
+  FORMAT U
+  OPCODE 0x37
+  OPERANDS rd, imm20
+  DESC Load upper immediate — places 20-bit immediate in upper 20 bits of rd
+  NOTE rd = imm20 << 12
+  CATEGORY Integer
+END
+
+INSTRUCTION AUIPC
+  FORMAT U
+  OPCODE 0x17
+  OPERANDS rd, imm20
+  DESC Add upper immediate to PC — forms PC-relative address
+  NOTE rd = PC + (imm20 << 12)
+  CATEGORY Integer
+END
+
+# =============================================================================
+# Logical Instructions
+# =============================================================================
+
+INSTRUCTION AND
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x7
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Bitwise AND
+  NOTE rd = rs1 & rs2
+  CATEGORY Logical
+END
+
+INSTRUCTION OR
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x6
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Bitwise OR
+  NOTE rd = rs1 | rs2
+  CATEGORY Logical
+END
+
+INSTRUCTION XOR
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x4
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Bitwise XOR
+  NOTE rd = rs1 ^ rs2
+  CATEGORY Logical
+END
+
+INSTRUCTION ANDI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x7
+  OPERANDS rd, rs1, imm12
+  DESC Bitwise AND with immediate
+  NOTE rd = rs1 & sext(imm12)
+  CATEGORY Logical
+  IMM true
+END
+
+INSTRUCTION ORI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x6
+  OPERANDS rd, rs1, imm12
+  DESC Bitwise OR with immediate
+  NOTE rd = rs1 | sext(imm12)
+  CATEGORY Logical
+  IMM true
+END
+
+INSTRUCTION XORI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x4
+  OPERANDS rd, rs1, imm12
+  DESC Bitwise XOR with immediate
+  NOTE rd = rs1 ^ sext(imm12)
+  CATEGORY Logical
+  IMM true
+END
+
+# =============================================================================
+# Shift Instructions
+# =============================================================================
+
+INSTRUCTION SLL
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x1
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Logical left shift by lower 5 bits of rs2
+  NOTE rd = rs1 << rs2[4:0]
+  CATEGORY Shift
+END
+
+INSTRUCTION SRL
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x5
+  FUNCT7 0x00
+  OPERANDS rd, rs1, rs2
+  DESC Logical right shift by lower 5 bits of rs2
+  NOTE rd = rs1 >> rs2[4:0]
+  CATEGORY Shift
+END
+
+INSTRUCTION SRA
+  FORMAT R
+  OPCODE 0x33
+  FUNCT3 0x5
+  FUNCT7 0x20
+  OPERANDS rd, rs1, rs2
+  DESC Arithmetic right shift by lower 5 bits of rs2
+  NOTE rd = rs1 >>> rs2[4:0]
+  CATEGORY Shift
+END
+
+INSTRUCTION SLLI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x1
+  OPERANDS rd, rs1, shamt5
+  DESC Logical left shift by immediate shift amount
+  NOTE rd = rs1 << shamt
+  CATEGORY Shift
+END
+
+INSTRUCTION SRLI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x5
+  OPERANDS rd, rs1, shamt5
+  DESC Logical right shift by immediate shift amount
+  NOTE rd = rs1 >> shamt
+  CATEGORY Shift
+END
+
+INSTRUCTION SRAI
+  FORMAT I
+  OPCODE 0x13
+  FUNCT3 0x5
+  OPERANDS rd, rs1, shamt5
+  DESC Arithmetic right shift by immediate shift amount
+  NOTE rd = rs1 >>> shamt
+  CATEGORY Shift
+END
+
+# =============================================================================
+# Memory Instructions
+# =============================================================================
+
+INSTRUCTION LB
+  FORMAT I
+  OPCODE 0x03
+  FUNCT3 0x0
+  OPERANDS rd, offset(rs1)
+  DESC Load byte (sign-extended)
+  NOTE rd = sext(MEM[rs1 + offset][7:0])
+  CATEGORY Memory
+END
+
+INSTRUCTION LH
+  FORMAT I
+  OPCODE 0x03
+  FUNCT3 0x1
+  OPERANDS rd, offset(rs1)
+  DESC Load halfword (sign-extended)
+  NOTE rd = sext(MEM[rs1 + offset][15:0])
+  CATEGORY Memory
+END
+
+INSTRUCTION LW
+  FORMAT I
+  OPCODE 0x03
+  FUNCT3 0x2
+  OPERANDS rd, offset(rs1)
+  DESC Load word
+  NOTE rd = MEM[rs1 + offset][31:0]
+  CATEGORY Memory
+END
+
+INSTRUCTION LBU
+  FORMAT I
+  OPCODE 0x03
+  FUNCT3 0x4
+  OPERANDS rd, offset(rs1)
+  DESC Load byte (zero-extended)
+  NOTE rd = MEM[rs1 + offset][7:0]
+  CATEGORY Memory
+END
+
+INSTRUCTION LHU
+  FORMAT I
+  OPCODE 0x03
+  FUNCT3 0x5
+  OPERANDS rd, offset(rs1)
+  DESC Load halfword (zero-extended)
+  NOTE rd = MEM[rs1 + offset][15:0]
+  CATEGORY Memory
+END
+
+INSTRUCTION SB
+  FORMAT S
+  OPCODE 0x23
+  FUNCT3 0x0
+  OPERANDS rs2, offset(rs1)
+  DESC Store byte
+  NOTE MEM[rs1 + offset][7:0] = rs2[7:0]
+  CATEGORY Memory
+END
+
+INSTRUCTION SH
+  FORMAT S
+  OPCODE 0x23
+  FUNCT3 0x1
+  OPERANDS rs2, offset(rs1)
+  DESC Store halfword
+  NOTE MEM[rs1 + offset][15:0] = rs2[15:0]
+  CATEGORY Memory
+END
+
+INSTRUCTION SW
+  FORMAT S
+  OPCODE 0x23
+  FUNCT3 0x2
+  OPERANDS rs2, offset(rs1)
+  DESC Store word
+  NOTE MEM[rs1 + offset][31:0] = rs2[31:0]
+  CATEGORY Memory
+END
+
+# =============================================================================
+# Branch Instructions
+# =============================================================================
+
+INSTRUCTION BEQ
+  FORMAT B
+  OPCODE 0x63
+  FUNCT3 0x0
+  OPERANDS rs1, rs2, label
+  DESC Branch equal
+  NOTE if (rs1 == rs2) PC += sext(offset)
+  CATEGORY Branch
+END
+
+INSTRUCTION BNE
+  FORMAT B
+  OPCODE 0x63
+  FUNCT3 0x1
+  OPERANDS rs1, rs2, label
+  DESC Branch not equal
+  NOTE if (rs1 != rs2) PC += sext(offset)
+  CATEGORY Branch
+END
+
+INSTRUCTION BLT
+  FORMAT B
+  OPCODE 0x63
+  FUNCT3 0x4
+  OPERANDS rs1, rs2, label
+  DESC Branch less than (signed)
+  NOTE if (rs1 < rs2) PC += sext(offset)
+  CATEGORY Branch
+END
+
+INSTRUCTION BGE
+  FORMAT B
+  OPCODE 0x63
+  FUNCT3 0x5
+  OPERANDS rs1, rs2, label
+  DESC Branch greater than or equal (signed)
+  NOTE if (rs1 >= rs2) PC += sext(offset)
+  CATEGORY Branch
+END
+
+INSTRUCTION BLTU
+  FORMAT B
+  OPCODE 0x63
+  FUNCT3 0x6
+  OPERANDS rs1, rs2, label
+  DESC Branch less than (unsigned)
+  NOTE if (rs1 < rs2) PC += sext(offset)
+  CATEGORY Branch
+END
+
+INSTRUCTION BGEU
+  FORMAT B
+  OPCODE 0x63
+  FUNCT3 0x7
+  OPERANDS rs1, rs2, label
+  DESC Branch greater than or equal (unsigned)
+  NOTE if (rs1 >= rs2) PC += sext(offset)
+  CATEGORY Branch
+END
+
+# =============================================================================
+# Jump Instructions
+# =============================================================================
+
+INSTRUCTION JAL
+  FORMAT J
+  OPCODE 0x6F
+  OPERANDS rd, label
+  DESC Jump and link — jump to PC+offset, save return address to rd
+  NOTE rd = PC + 4; PC += sext(offset)
+  CATEGORY Jump
+END
+
+INSTRUCTION JALR
+  FORMAT I
+  OPCODE 0x67
+  FUNCT3 0x0
+  OPERANDS rd, rs1, offset
+  DESC Jump and link register — jump to rs1+offset, save return address
+  NOTE rd = PC + 4; PC = (rs1 + sext(offset)) & ~1
+  CATEGORY Jump
+END
+
+# =============================================================================
+# Synchronization Instructions
+# =============================================================================
+
+INSTRUCTION FENCE
+  FORMAT I
+  OPCODE 0x0F
+  FUNCT3 0x0
+  OPERANDS pred, succ
+  DESC Memory ordering fence
+  NOTE Orders memory accesses as specified by pred and succ fields
+  CATEGORY Synchronization
+END
+
+INSTRUCTION FENCEI
+  FORMAT I
+  OPCODE 0x0F
+  FUNCT3 0x1
+  OPERANDS —
+  DESC Instruction fence — synchronizes instruction and data streams
+  NOTE Flushes instruction cache after data writes
+  CATEGORY Synchronization
+END
+
+# =============================================================================
+# System Instructions
+# =============================================================================
+
+INSTRUCTION ECALL
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x0
+  OPERANDS —
+  DESC Environment call — raises a system call exception
+  NOTE Traps to the configured exception handler
+  CATEGORY System
+END
+
+INSTRUCTION EBREAK
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x0
+  OPERANDS —
+  DESC Breakpoint — raises a breakpoint exception
+  NOTE Used by debuggers to halt program execution
+  CATEGORY System
+END
+
+INSTRUCTION CSRRW
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x1
+  OPERANDS rd, csr, rs1
+  DESC Atomic read/write CSR — writes rs1 to CSR, returns old value in rd
+  NOTE rd = CSR[csr]; CSR[csr] = rs1
+  CATEGORY System
+END
+
+INSTRUCTION CSRRS
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x2
+  OPERANDS rd, csr, rs1
+  DESC Atomic read and set bits in CSR
+  NOTE rd = CSR[csr]; CSR[csr] |= rs1
+  CATEGORY System
+END
+
+INSTRUCTION CSRRC
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x3
+  OPERANDS rd, csr, rs1
+  DESC Atomic read and clear bits in CSR
+  NOTE rd = CSR[csr]; CSR[csr] &= ~rs1
+  CATEGORY System
+END
+
+INSTRUCTION CSRRWI
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x5
+  OPERANDS rd, csr, uimm5
+  DESC Atomic read/write CSR with immediate
+  NOTE rd = CSR[csr]; CSR[csr] = zimm
+  CATEGORY System
+END
+
+INSTRUCTION CSRRSI
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x6
+  OPERANDS rd, csr, uimm5
+  DESC Atomic read and set bits in CSR with immediate
+  NOTE rd = CSR[csr]; CSR[csr] |= zimm
+  CATEGORY System
+END
+
+INSTRUCTION CSRRCI
+  FORMAT I
+  OPCODE 0x73
+  FUNCT3 0x7
+  OPERANDS rd, csr, uimm5
+  DESC Atomic read and clear bits in CSR with immediate
+  NOTE rd = CSR[csr]; CSR[csr] &= ~zimm
+  CATEGORY System
+END
diff --git a/gen/docs/isa_defs/registers.isa b/gen/docs/isa_defs/registers.isa
new file mode 100644
index 0000000..baa8124
--- /dev/null
+++ b/gen/docs/isa_defs/registers.isa
@@ -0,0 +1,289 @@
+# Fyntv Register Definitions
+
+REGISTER x0
+  ABBR zero
+  DESC Always-zero register — reads return 0, writes are discarded
+  PRESERVE false
+  CALLER false
+  ARG false
+  INDEX 0
+END
+
+REGISTER x1
+  ABBR ra
+  DESC Return address link register
+  PRESERVE false
+  CALLER false
+  ARG false
+  INDEX 1
+END
+
+REGISTER x2
+  ABBR sp
+  DESC Stack pointer
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 2
+END
+
+REGISTER x3
+  ABBR gp
+  DESC Global pointer
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 3
+END
+
+REGISTER x4
+  ABBR tp
+  DESC Thread pointer
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 4
+END
+
+REGISTER x5
+  ABBR t0
+  DESC Temporary register 0
+  PRESERVE false
+  CALLER true
+  ARG false
+  INDEX 5
+END
+
+REGISTER x6
+  ABBR t1
+  DESC Temporary register 1
+  PRESERVE false
+  CALLER true
+  ARG false
+  INDEX 6
+END
+
+REGISTER x7
+  ABBR t2
+  DESC Temporary register 2
+  PRESERVE false
+  CALLER true
+  ARG false
+  INDEX 7
+END
+
+REGISTER x8
+  ABBR s0
+  DESC Saved register 0 / frame pointer
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 8
+END
+
+REGISTER x9
+  ABBR s1
+  DESC Saved register 1
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 9
+END
+
+REGISTER x10
+  ABBR a0
+  DESC Function argument 0 / return value 0
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 10
+END
+
+REGISTER x11
+  ABBR a1
+  DESC Function argument 1 / return value 1
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 11
+END
+
+REGISTER x12
+  ABBR a2
+  DESC Function argument 2
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 12
+END
+
+REGISTER x13
+  ABBR a3
+  DESC Function argument 3
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 13
+END
+
+REGISTER x14
+  ABBR a4
+  DESC Function argument 4
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 14
+END
+
+REGISTER x15
+  ABBR a5
+  DESC Function argument 5
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 15
+END
+
+REGISTER x16
+  ABBR a6
+  DESC Function argument 6
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 16
+END
+
+REGISTER x17
+  ABBR a7
+  DESC Function argument 7
+  PRESERVE false
+  CALLER true
+  ARG true
+  INDEX 17
+END
+
+REGISTER x18
+  ABBR s2
+  DESC Saved register 2
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 18
+END
+
+REGISTER x19
+  ABBR s3
+  DESC Saved register 3
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 19
+END
+
+REGISTER x20
+  ABBR s4
+  DESC Saved register 4
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 20
+END
+
+REGISTER x21
+  ABBR s5
+  DESC Saved register 5
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 21
+END
+
+REGISTER x22
+  ABBR s6
+  DESC Saved register 6
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 22
+END
+
+REGISTER x23
+  ABBR s7
+  DESC Saved register 7
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 23
+END
+
+REGISTER x24
+  ABBR s8
+  DESC Saved register 8
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 24
+END
+
+REGISTER x25
+  ABBR s9
+  DESC Saved register 9
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 25
+END
+
+REGISTER x26
+  ABBR s10
+  DESC Saved register 10
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 26
+END
+
+REGISTER x27
+  ABBR s11
+  DESC Saved register 11
+  PRESERVE true
+  CALLER false
+  ARG false
+  INDEX 27
+END
+
+REGISTER x28
+  ABBR t3
+  DESC Temporary register 3
+  PRESERVE false
+  CALLER true
+  ARG false
+  INDEX 28
+END
+
+REGISTER x29
+  ABBR t4
+  DESC Temporary register 4
+  PRESERVE false
+  CALLER true
+  ARG false
+  INDEX 29
+END
+
+REGISTER x30
+  ABBR t5
+  DESC Temporary register 5
+  PRESERVE false
+  CALLER true
+  ARG false
+  INDEX 30
+END
+
+REGISTER x31
+  ABBR t6
+  DESC Temporary register 6
+  PRESERVE false
+  CALLER true
+  ARG false
+  INDEX 31
+END