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<title>Fyntv ISA Reference Manual</title>
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<h1>Fyntv Instruction Set Architecture</h1>
<p class="subtitle">Reference Manual</p>
<p><strong>Version:</strong> 0.0.0.1 &nbsp;|&nbsp; <strong>Date:</strong> June 2026</p>
</header>
<section id="registers">
<h2>Registers</h2>
<table><thead><tr><th>Register</th><th>ABI Name</th><th>Description</th><th>Saved</th></tr></thead><tbody>
<tr><td>x0</td><td>zero</td><td>Always-zero register — reads return 0, writes are discarded</td><td>No</td></tr>
<tr><td>x1</td><td>ra</td><td>Return address link register</td><td>No</td></tr>
<tr><td>x2</td><td>sp</td><td>Stack pointer</td><td>Yes</td></tr>
<tr><td>x3</td><td>gp</td><td>Global pointer</td><td>Yes</td></tr>
<tr><td>x4</td><td>tp</td><td>Thread pointer</td><td>Yes</td></tr>
<tr><td>x5</td><td>t0</td><td>Temporary register 0</td><td>No</td></tr>
<tr><td>x6</td><td>t1</td><td>Temporary register 1</td><td>No</td></tr>
<tr><td>x7</td><td>t2</td><td>Temporary register 2</td><td>No</td></tr>
<tr><td>x8</td><td>s0</td><td>Saved register 0 / frame pointer</td><td>Yes</td></tr>
<tr><td>x9</td><td>s1</td><td>Saved register 1</td><td>Yes</td></tr>
<tr><td>x10</td><td>a0</td><td>Function argument 0 / return value 0</td><td>No</td></tr>
<tr><td>x11</td><td>a1</td><td>Function argument 1 / return value 1</td><td>No</td></tr>
<tr><td>x12</td><td>a2</td><td>Function argument 2</td><td>No</td></tr>
<tr><td>x13</td><td>a3</td><td>Function argument 3</td><td>No</td></tr>
<tr><td>x14</td><td>a4</td><td>Function argument 4</td><td>No</td></tr>
<tr><td>x15</td><td>a5</td><td>Function argument 5</td><td>No</td></tr>
<tr><td>x16</td><td>a6</td><td>Function argument 6</td><td>No</td></tr>
<tr><td>x17</td><td>a7</td><td>Function argument 7</td><td>No</td></tr>
<tr><td>x18</td><td>s2</td><td>Saved register 2</td><td>Yes</td></tr>
<tr><td>x19</td><td>s3</td><td>Saved register 3</td><td>Yes</td></tr>
<tr><td>x20</td><td>s4</td><td>Saved register 4</td><td>Yes</td></tr>
<tr><td>x21</td><td>s5</td><td>Saved register 5</td><td>Yes</td></tr>
<tr><td>x22</td><td>s6</td><td>Saved register 6</td><td>Yes</td></tr>
<tr><td>x23</td><td>s7</td><td>Saved register 7</td><td>Yes</td></tr>
<tr><td>x24</td><td>s8</td><td>Saved register 8</td><td>Yes</td></tr>
<tr><td>x25</td><td>s9</td><td>Saved register 9</td><td>Yes</td></tr>
<tr><td>x26</td><td>s10</td><td>Saved register 10</td><td>Yes</td></tr>
<tr><td>x27</td><td>s11</td><td>Saved register 11</td><td>Yes</td></tr>
<tr><td>x28</td><td>t3</td><td>Temporary register 3</td><td>No</td></tr>
<tr><td>x29</td><td>t4</td><td>Temporary register 4</td><td>No</td></tr>
<tr><td>x30</td><td>t5</td><td>Temporary register 5</td><td>No</td></tr>
<tr><td>x31</td><td>t6</td><td>Temporary register 6</td><td>No</td></tr>
</tbody></table>
</section>
<section id="instructions">
<h2>Instruction Set</h2>
<table><thead><tr><th>Mnemonic</th><th>Format</th><th>Opcode</th><th>Operands</th><th>Description</th></tr></thead><tbody>
<tr><td><code>ADD</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Add registers</td></tr>
<tr><td><code>SUB</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Subtract registers</td></tr>
<tr><td><code>ADDI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, imm12</code></td><td>Add sign-extended 12-bit immediate to register rs1</td></tr>
<tr><td><code>SLT</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Set if rs1 is less than rs2 (signed)</td></tr>
<tr><td><code>SLTU</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Set if rs1 is less than rs2 (unsigned)</td></tr>
<tr><td><code>SLTI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, imm12</code></td><td>Set if rs1 is less than immediate (signed)</td></tr>
<tr><td><code>SLTIU</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, imm12</code></td><td>Set if rs1 is less than immediate (unsigned)</td></tr>
<tr><td><code>LUI</code></td><td>U</td><td><code>0x37</code></td><td><code>rd, imm20</code></td><td>Load upper immediate — places 20-bit immediate in upper 20 bits of rd</td></tr>
<tr><td><code>AUIPC</code></td><td>U</td><td><code>0x17</code></td><td><code>rd, imm20</code></td><td>Add upper immediate to PC — forms PC-relative address</td></tr>
<tr><td><code>AND</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Bitwise AND</td></tr>
<tr><td><code>OR</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Bitwise OR</td></tr>
<tr><td><code>XOR</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Bitwise XOR</td></tr>
<tr><td><code>ANDI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, imm12</code></td><td>Bitwise AND with immediate</td></tr>
<tr><td><code>ORI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, imm12</code></td><td>Bitwise OR with immediate</td></tr>
<tr><td><code>XORI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, imm12</code></td><td>Bitwise XOR with immediate</td></tr>
<tr><td><code>SLL</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Logical left shift by lower 5 bits of rs2</td></tr>
<tr><td><code>SRL</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Logical right shift by lower 5 bits of rs2</td></tr>
<tr><td><code>SRA</code></td><td>R</td><td><code>0x33</code></td><td><code>rd, rs1, rs2</code></td><td>Arithmetic right shift by lower 5 bits of rs2</td></tr>
<tr><td><code>SLLI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, shamt5</code></td><td>Logical left shift by immediate shift amount</td></tr>
<tr><td><code>SRLI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, shamt5</code></td><td>Logical right shift by immediate shift amount</td></tr>
<tr><td><code>SRAI</code></td><td>I</td><td><code>0x13</code></td><td><code>rd, rs1, shamt5</code></td><td>Arithmetic right shift by immediate shift amount</td></tr>
<tr><td><code>LB</code></td><td>I</td><td><code>0x03</code></td><td><code>rd, offset(rs1)</code></td><td>Load byte (sign-extended)</td></tr>
<tr><td><code>LH</code></td><td>I</td><td><code>0x03</code></td><td><code>rd, offset(rs1)</code></td><td>Load halfword (sign-extended)</td></tr>
<tr><td><code>LW</code></td><td>I</td><td><code>0x03</code></td><td><code>rd, offset(rs1)</code></td><td>Load word</td></tr>
<tr><td><code>LBU</code></td><td>I</td><td><code>0x03</code></td><td><code>rd, offset(rs1)</code></td><td>Load byte (zero-extended)</td></tr>
<tr><td><code>LHU</code></td><td>I</td><td><code>0x03</code></td><td><code>rd, offset(rs1)</code></td><td>Load halfword (zero-extended)</td></tr>
<tr><td><code>SB</code></td><td>S</td><td><code>0x23</code></td><td><code>rs2, offset(rs1)</code></td><td>Store byte</td></tr>
<tr><td><code>SH</code></td><td>S</td><td><code>0x23</code></td><td><code>rs2, offset(rs1)</code></td><td>Store halfword</td></tr>
<tr><td><code>SW</code></td><td>S</td><td><code>0x23</code></td><td><code>rs2, offset(rs1)</code></td><td>Store word</td></tr>
<tr><td><code>BEQ</code></td><td>B</td><td><code>0x63</code></td><td><code>rs1, rs2, label</code></td><td>Branch equal</td></tr>
<tr><td><code>BNE</code></td><td>B</td><td><code>0x63</code></td><td><code>rs1, rs2, label</code></td><td>Branch not equal</td></tr>
<tr><td><code>BLT</code></td><td>B</td><td><code>0x63</code></td><td><code>rs1, rs2, label</code></td><td>Branch less than (signed)</td></tr>
<tr><td><code>BGE</code></td><td>B</td><td><code>0x63</code></td><td><code>rs1, rs2, label</code></td><td>Branch greater than or equal (signed)</td></tr>
<tr><td><code>BLTU</code></td><td>B</td><td><code>0x63</code></td><td><code>rs1, rs2, label</code></td><td>Branch less than (unsigned)</td></tr>
<tr><td><code>BGEU</code></td><td>B</td><td><code>0x63</code></td><td><code>rs1, rs2, label</code></td><td>Branch greater than or equal (unsigned)</td></tr>
<tr><td><code>JAL</code></td><td>J</td><td><code>0x6F</code></td><td><code>rd, label</code></td><td>Jump and link — jump to PC+offset, save return address to rd</td></tr>
<tr><td><code>JALR</code></td><td>I</td><td><code>0x67</code></td><td><code>rd, rs1, offset</code></td><td>Jump and link register — jump to rs1+offset, save return address</td></tr>
<tr><td><code>FENCE</code></td><td>I</td><td><code>0x0F</code></td><td><code>pred, succ</code></td><td>Memory ordering fence</td></tr>
<tr><td><code>FENCEI</code></td><td>I</td><td><code>0x0F</code></td><td><code>—</code></td><td>Instruction fence — synchronizes instruction and data streams</td></tr>
<tr><td><code>ECALL</code></td><td>I</td><td><code>0x73</code></td><td><code>—</code></td><td>Environment call — raises a system call exception</td></tr>
<tr><td><code>EBREAK</code></td><td>I</td><td><code>0x73</code></td><td><code>—</code></td><td>Breakpoint — raises a breakpoint exception</td></tr>
<tr><td><code>CSRRW</code></td><td>I</td><td><code>0x73</code></td><td><code>rd, csr, rs1</code></td><td>Atomic read/write CSR — writes rs1 to CSR, returns old value in rd</td></tr>
<tr><td><code>CSRRS</code></td><td>I</td><td><code>0x73</code></td><td><code>rd, csr, rs1</code></td><td>Atomic read and set bits in CSR</td></tr>
<tr><td><code>CSRRC</code></td><td>I</td><td><code>0x73</code></td><td><code>rd, csr, rs1</code></td><td>Atomic read and clear bits in CSR</td></tr>
<tr><td><code>CSRRWI</code></td><td>I</td><td><code>0x73</code></td><td><code>rd, csr, uimm5</code></td><td>Atomic read/write CSR with immediate</td></tr>
<tr><td><code>CSRRSI</code></td><td>I</td><td><code>0x73</code></td><td><code>rd, csr, uimm5</code></td><td>Atomic read and set bits in CSR with immediate</td></tr>
<tr><td><code>CSRRCI</code></td><td>I</td><td><code>0x73</code></td><td><code>rd, csr, uimm5</code></td><td>Atomic read and clear bits in CSR with immediate</td></tr>
</tbody></table>
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