path: root/gen/docs/isa_defs/instructions.isa

# Fyntv Core Integer Instructions

INSTRUCTION ADD
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x0
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Add registers
  NOTE rd = rs1 + rs2
  CATEGORY Integer
END

INSTRUCTION SUB
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x0 
  FUNCT7 0x20
  OPERANDS rd, rs1, rs2
  DESC Subtract registers
  NOTE rd = rs1 - rs2
  CATEGORY Integer
END

INSTRUCTION ADDI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x0
  OPERANDS rd, rs1, imm12
  DESC Add sign-extended 12-bit immediate to register rs1
  NOTE rd = rs1 + sext(imm12)
  CATEGORY Integer
  IMM true
END

INSTRUCTION SLT
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x2
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Set if rs1 is less than rs2 (signed)
  NOTE rd = (rs1 < rs2) ? 1 : 0
  CATEGORY Integer
END

INSTRUCTION SLTU
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x3
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Set if rs1 is less than rs2 (unsigned)
  NOTE rd = (rs1 < rs2) ? 1 : 0
  CATEGORY Integer
END

INSTRUCTION SLTI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x2
  OPERANDS rd, rs1, imm12
  DESC Set if rs1 is less than immediate (signed)
  NOTE rd = (rs1 < sext(imm12)) ? 1 : 0
  CATEGORY Integer
  IMM true
END

INSTRUCTION SLTIU
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x3
  OPERANDS rd, rs1, imm12
  DESC Set if rs1 is less than immediate (unsigned)
  NOTE rd = (rs1 < sext(imm12)) ? 1 : 0
  CATEGORY Integer
  IMM true
END

INSTRUCTION LUI
  FORMAT U
  OPCODE 0x37
  OPERANDS rd, imm20
  DESC Load upper immediate — places 20-bit immediate in upper 20 bits of rd
  NOTE rd = imm20 << 12
  CATEGORY Integer
END

INSTRUCTION AUIPC
  FORMAT U
  OPCODE 0x17
  OPERANDS rd, imm20
  DESC Add upper immediate to PC — forms PC-relative address
  NOTE rd = PC + (imm20 << 12)
  CATEGORY Integer
END

# =============================================================================
# Logical Instructions
# =============================================================================

INSTRUCTION AND
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x7
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Bitwise AND
  NOTE rd = rs1 & rs2
  CATEGORY Logical
END

INSTRUCTION OR
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x6
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Bitwise OR
  NOTE rd = rs1 | rs2
  CATEGORY Logical
END

INSTRUCTION XOR
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x4
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Bitwise XOR
  NOTE rd = rs1 ^ rs2
  CATEGORY Logical
END

INSTRUCTION ANDI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x7
  OPERANDS rd, rs1, imm12
  DESC Bitwise AND with immediate
  NOTE rd = rs1 & sext(imm12)
  CATEGORY Logical
  IMM true
END

INSTRUCTION ORI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x6
  OPERANDS rd, rs1, imm12
  DESC Bitwise OR with immediate
  NOTE rd = rs1 | sext(imm12)
  CATEGORY Logical
  IMM true
END

INSTRUCTION XORI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x4
  OPERANDS rd, rs1, imm12
  DESC Bitwise XOR with immediate
  NOTE rd = rs1 ^ sext(imm12)
  CATEGORY Logical
  IMM true
END

# =============================================================================
# Shift Instructions
# =============================================================================

INSTRUCTION SLL
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x1
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Logical left shift by lower 5 bits of rs2
  NOTE rd = rs1 << rs2[4:0]
  CATEGORY Shift
END

INSTRUCTION SRL
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x5
  FUNCT7 0x00
  OPERANDS rd, rs1, rs2
  DESC Logical right shift by lower 5 bits of rs2
  NOTE rd = rs1 >> rs2[4:0]
  CATEGORY Shift
END

INSTRUCTION SRA
  FORMAT R
  OPCODE 0x33
  FUNCT3 0x5
  FUNCT7 0x20
  OPERANDS rd, rs1, rs2
  DESC Arithmetic right shift by lower 5 bits of rs2
  NOTE rd = rs1 >>> rs2[4:0]
  CATEGORY Shift
END

INSTRUCTION SLLI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x1
  OPERANDS rd, rs1, shamt5
  DESC Logical left shift by immediate shift amount
  NOTE rd = rs1 << shamt
  CATEGORY Shift
END

INSTRUCTION SRLI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x5
  OPERANDS rd, rs1, shamt5
  DESC Logical right shift by immediate shift amount
  NOTE rd = rs1 >> shamt
  CATEGORY Shift
END

INSTRUCTION SRAI
  FORMAT I
  OPCODE 0x13
  FUNCT3 0x5
  OPERANDS rd, rs1, shamt5
  DESC Arithmetic right shift by immediate shift amount
  NOTE rd = rs1 >>> shamt
  CATEGORY Shift
END

# =============================================================================
# Memory Instructions
# =============================================================================

INSTRUCTION LB
  FORMAT I
  OPCODE 0x03
  FUNCT3 0x0
  OPERANDS rd, offset(rs1)
  DESC Load byte (sign-extended)
  NOTE rd = sext(MEM[rs1 + offset][7:0])
  CATEGORY Memory
END

INSTRUCTION LH
  FORMAT I
  OPCODE 0x03
  FUNCT3 0x1
  OPERANDS rd, offset(rs1)
  DESC Load halfword (sign-extended)
  NOTE rd = sext(MEM[rs1 + offset][15:0])
  CATEGORY Memory
END

INSTRUCTION LW
  FORMAT I
  OPCODE 0x03
  FUNCT3 0x2
  OPERANDS rd, offset(rs1)
  DESC Load word
  NOTE rd = MEM[rs1 + offset][31:0]
  CATEGORY Memory
END

INSTRUCTION LBU
  FORMAT I
  OPCODE 0x03
  FUNCT3 0x4
  OPERANDS rd, offset(rs1)
  DESC Load byte (zero-extended)
  NOTE rd = MEM[rs1 + offset][7:0]
  CATEGORY Memory
END

INSTRUCTION LHU
  FORMAT I
  OPCODE 0x03
  FUNCT3 0x5
  OPERANDS rd, offset(rs1)
  DESC Load halfword (zero-extended)
  NOTE rd = MEM[rs1 + offset][15:0]
  CATEGORY Memory
END

INSTRUCTION SB
  FORMAT S
  OPCODE 0x23
  FUNCT3 0x0
  OPERANDS rs2, offset(rs1)
  DESC Store byte
  NOTE MEM[rs1 + offset][7:0] = rs2[7:0]
  CATEGORY Memory
END

INSTRUCTION SH
  FORMAT S
  OPCODE 0x23
  FUNCT3 0x1
  OPERANDS rs2, offset(rs1)
  DESC Store halfword
  NOTE MEM[rs1 + offset][15:0] = rs2[15:0]
  CATEGORY Memory
END

INSTRUCTION SW
  FORMAT S
  OPCODE 0x23
  FUNCT3 0x2
  OPERANDS rs2, offset(rs1)
  DESC Store word
  NOTE MEM[rs1 + offset][31:0] = rs2[31:0]
  CATEGORY Memory
END

# =============================================================================
# Branch Instructions
# =============================================================================

INSTRUCTION BEQ
  FORMAT B
  OPCODE 0x63
  FUNCT3 0x0
  OPERANDS rs1, rs2, label
  DESC Branch equal
  NOTE if (rs1 == rs2) PC += sext(offset)
  CATEGORY Branch
END

INSTRUCTION BNE
  FORMAT B
  OPCODE 0x63
  FUNCT3 0x1
  OPERANDS rs1, rs2, label
  DESC Branch not equal
  NOTE if (rs1 != rs2) PC += sext(offset)
  CATEGORY Branch
END

INSTRUCTION BLT
  FORMAT B
  OPCODE 0x63
  FUNCT3 0x4
  OPERANDS rs1, rs2, label
  DESC Branch less than (signed)
  NOTE if (rs1 < rs2) PC += sext(offset)
  CATEGORY Branch
END

INSTRUCTION BGE
  FORMAT B
  OPCODE 0x63
  FUNCT3 0x5
  OPERANDS rs1, rs2, label
  DESC Branch greater than or equal (signed)
  NOTE if (rs1 >= rs2) PC += sext(offset)
  CATEGORY Branch
END

INSTRUCTION BLTU
  FORMAT B
  OPCODE 0x63
  FUNCT3 0x6
  OPERANDS rs1, rs2, label
  DESC Branch less than (unsigned)
  NOTE if (rs1 < rs2) PC += sext(offset)
  CATEGORY Branch
END

INSTRUCTION BGEU
  FORMAT B
  OPCODE 0x63
  FUNCT3 0x7
  OPERANDS rs1, rs2, label
  DESC Branch greater than or equal (unsigned)
  NOTE if (rs1 >= rs2) PC += sext(offset)
  CATEGORY Branch
END

# =============================================================================
# Jump Instructions
# =============================================================================

INSTRUCTION JAL
  FORMAT J
  OPCODE 0x6F
  OPERANDS rd, label
  DESC Jump and link — jump to PC+offset, save return address to rd
  NOTE rd = PC + 4; PC += sext(offset)
  CATEGORY Jump
END

INSTRUCTION JALR
  FORMAT I
  OPCODE 0x67
  FUNCT3 0x0
  OPERANDS rd, rs1, offset
  DESC Jump and link register — jump to rs1+offset, save return address
  NOTE rd = PC + 4; PC = (rs1 + sext(offset)) & ~1
  CATEGORY Jump
END

# =============================================================================
# Synchronization Instructions
# =============================================================================

INSTRUCTION FENCE
  FORMAT I
  OPCODE 0x0F
  FUNCT3 0x0
  OPERANDS pred, succ
  DESC Memory ordering fence
  NOTE Orders memory accesses as specified by pred and succ fields
  CATEGORY Synchronization
END

INSTRUCTION FENCEI
  FORMAT I
  OPCODE 0x0F
  FUNCT3 0x1
  OPERANDS —
  DESC Instruction fence — synchronizes instruction and data streams
  NOTE Flushes instruction cache after data writes
  CATEGORY Synchronization
END

# =============================================================================
# System Instructions
# =============================================================================

INSTRUCTION ECALL
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x0
  OPERANDS —
  DESC Environment call — raises a system call exception
  NOTE Traps to the configured exception handler
  CATEGORY System
END

INSTRUCTION EBREAK
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x0
  OPERANDS —
  DESC Breakpoint — raises a breakpoint exception
  NOTE Used by debuggers to halt program execution
  CATEGORY System
END

INSTRUCTION CSRRW
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x1
  OPERANDS rd, csr, rs1
  DESC Atomic read/write CSR — writes rs1 to CSR, returns old value in rd
  NOTE rd = CSR[csr]; CSR[csr] = rs1
  CATEGORY System
END

INSTRUCTION CSRRS
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x2
  OPERANDS rd, csr, rs1
  DESC Atomic read and set bits in CSR
  NOTE rd = CSR[csr]; CSR[csr] |= rs1
  CATEGORY System
END

INSTRUCTION CSRRC
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x3
  OPERANDS rd, csr, rs1
  DESC Atomic read and clear bits in CSR
  NOTE rd = CSR[csr]; CSR[csr] &= ~rs1
  CATEGORY System
END

INSTRUCTION CSRRWI
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x5
  OPERANDS rd, csr, uimm5
  DESC Atomic read/write CSR with immediate
  NOTE rd = CSR[csr]; CSR[csr] = zimm
  CATEGORY System
END

INSTRUCTION CSRRSI
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x6
  OPERANDS rd, csr, uimm5
  DESC Atomic read and set bits in CSR with immediate
  NOTE rd = CSR[csr]; CSR[csr] |= zimm
  CATEGORY System
END

INSTRUCTION CSRRCI
  FORMAT I
  OPCODE 0x73
  FUNCT3 0x7
  OPERANDS rd, csr, uimm5
  DESC Atomic read and clear bits in CSR with immediate
  NOTE rd = CSR[csr]; CSR[csr] &= ~zimm
  CATEGORY System
END